1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more specifically, to a stacked capacitor type semiconductor memory device capable of inputting/outputting arbitrary memory data at random and to the method for making the same.
2. Description of the Background Art
Recently, semiconductor memory devices are in great demand as information machines such as computers have come to be widely used. Semiconductor memory devices having large memory capacitances and capable of high speed operation are desired. Accordingly, the technology in association with the higher degree of integration, the high speed responsiveness and higher reliability of the semiconductor memory devices has been developed.
A DRAM (Dynamic Random Access Memory) is a semiconductor memory device capable of inputting/outputting memory data at random. Generally, a DRAM comprises a memory cell array which is a memory region storing a large number of memory data and peripheral circuits required for external input/output. FIG. 5 is a block diagram showing a structure of a common DRAM. Referring to the figure, the DRAM 50 comprises a memory cell array 51 for storing data signals representing memory information, a row and column address buffer 52 for externally receiving an address signal for selecting a memory cell constituting a unit memory circuit, a row decoder 53 and a column decoder 54 for designating the memory cell by interpreting the address signal, a sense refresh amplifier 55 for amplifying the signals stored in the designated memory cell to read the same, a data in buffer 56 and a data output buffer 57 for data input/output, and a clock generator 58 for generating clock signals.
The memory cell array 51 occupying a large area on a semiconductor chip is formed of an arrangement of a plurality of memory cells each storing unit memory data. FIG. 6 is an equivalent circuit diagram of 4 bits of memory cells constituting the memory cell array 51. The shown memory cell is a 1-transistor 1-capacitor type memory cell comprising one MOS (Metal Oxide Semiconductor) transistor and one capacitor element connected thereto. The memory cell structure of this type is simple and it enables improvement of the degree of integration of the memory cell array, so that the structure is widely used for DRAMs having large capacitances.
FIG. 7 is a plan view showing one example of a stacked capacitor type memory cell array of a DRAM. FIGS. 8A to 8D are cross sectional views taken along the line VIII--VIII of FIG. 7 showing, in order, the steps of manufacturing the structure. Such stacked type memory cells of the DRAMs are manufactured in accordance with the following manufacturing steps.
First, as shown in FIG. 8A, a thick field oxide film 2 is formed on a surface of a semiconductor substrate 1 to surround an element forming region by LOCOS (Local Oxidation of Silicon) method. Thereafter, patterned gate electrodes (word lines) 4a and 4b are formed on the surface of the semiconductor substrate 1 with a thin oxide film 3 interposed therebetween. Impurity diffused regions 5a and 5b are formed on the surfaces of the semiconductor substrate 1 on both sides of the gate electrode 4a formed on the surface of the semiconductor substrate 1. The periphery of the gate electrodes 4a and 4b are covered with an insulating film 6.
Next, as shown in FIG. 8B, a conductive polysilicon layer 7 is stacked on the surface of the insulating film 6.
Further, as shown in FIG. 8C, the polysilicon layer 7 is patterned to a prescribed pattern by anisotropic etching such as reactive ion etching. An anisotropic etching takes place for example by directing ions onto the surface, of polysilicon layer 7. Reaction between the ions and the layer proceeds, and the layer is etched by a common thickness in the single direction into the layer. The patterned polysilicon layer 7 constitutes a lower electrode 8 of the capacitor. The surface area of the lower electrode 8 formed of polysilicon should be as large as possible to increase the capacitance of the capacitor. Therefore, the polysilicon layer 7 deposited in the step of FIG. 8B is made thick. The etching method employed for patterning is anisotropic etching in which etching is not effected in the horizontal direction to the main surface of the substrate. However, due to the anisotropic etching, wherein a common thickness of polysilicon layer 7 is etched throughout, portions of the polysilicon layer 7 are left as residues 9 in the regions where the surface of the semiconductor substrate 1 or the surface of the field oxide film 2 intersects the side regions of the gate electrode 4. The regions where the residues 9 are formed are shown in the plan view of FIG. 7.
Thereafter, as shown in FIG. 8D, a silicon nitride film 10 constituting a dielectric layer of the capacitor is deposited, a polysilicon layer constituting an upper electrode 11 is stacked and the capacitor is formed by patterning.
In the above described conventional method for manufacturing stacked type DRAMs, the residue 9 of the conductive polysilicon formed in the step of manufacturing the lower electrode 8 shown in FIG. 8C is a problem. Namely, as shown in FIG. 7, the residues 9 are formed to cause short circuit between electrodes of the capacitors of the memory cells formed spaced apart from each other in the horizontal direction. Therefore, in operation, short circuits are caused by the conductive residues 9 between the memory cells, resulting in malfunctions and the like.
A prior art solution of the problem derived from the residues of etching will be described in the following. A structure is shown in Japanese patent Laying-Open No. 6853/1987 in which the capacitance of the capacitor is further increased compared with the above described stacked type DRAM. FIGS. 9A and 9B are cross sectional views showing the cross sectional structure of the memory cell of a DRAM shown in this gazette in accordance with a representative manufacturing process. In this example, an insulating film 6 covering a gate electrode 4 of a transfer gate transistor 13 is made thick, and a capacitor 14 is formed utilizing an opening portion 12 and the surface thereof selectively formed in the insulating film 6. Important manufacturing steps will be described in the following.
First, as shown in FIG. 9A, an insulating film 6 is deposited thick on a semiconductor substrate 1 on which a transfer gate transistor 13 is formed. The surface of the film is made flat. Thereafter, the insulating film 6 is patterned, and opening portions 12 are formed on the surfaces of impurity diffuse regions 5a and 5b formed on the surface of the semiconductors substrate 1.
Thereafter, as shown in FIG. 9B, a capacitor 14 is formed in the opening portion 12 of the insulating film 6 and on the surface of the insulating film 6. The capacitor 14 comprises a lower electrode 8 which is in direct contact with the impurity diffused region 5a, an upper electrode 11, and a dielectric layer 10 sandwiched by the lower electrode 8 and the upper electrode 11. The lower electrode 8 terminates on a flat surface of the insulating film 6. Therefore, in the step of patterning the lower electrode 8, there will be no residue since no portion of the electrode 8 is left in etching. Namely, the opening portion 12 is formed only on the surfaces of the impurity diffused regions 5a and 5b. The opening portion 12 is not formed between the impurity regions adjacent to each other with the field insulating film 2 interposed therebetween. Therefore, there is no residue of etching formed over the adjacent impurity regions. In addition, the capacitor 14 curves from the surface of the insulating film 6 along the inner wall of the opening portion 12. Consequently, the surface area of the capacitive coupling becomes large, increasing the capacitance.
However, the method for manufacturing the memory cell having such structure comprises a step of patterning for forming the opening portion 12 in the insulating film 6 as shown in FIG. 9A. In this step, the photolithography method is used in general. This method comprises a step of aligning pattern mask for forming the opening portion 12. Since there should be a margin in consideration of the error in aligning masks, the width of the diffusion of the impurity diffuse region 5a naturally becomes wide. The width of diffusion of the impurity diffused region 5a is a factor preventing minimization of the memory cell structure.
As described above, in the memory cell structure of the DRAM, the following points are desired, namely, the gate structure of the transfer gate transistor constituting the memory cell should be minimized, and the junction area of the capacitor should be increased to maintain and further to increase the capacitance of the capacitor which naturally decreases as the transistor structure is minimized. However, the conventional method comprises disadvantages such as short circuits between capacitors derived from the manufacturing process and the enlargement of the impurity diffused region of the transistor derived from the increase of the capacitance of the capacitor.